1. Field of the Invention
The present invention relates to a computer system having a Peripheral Component Interconnect (PCI) bus system and, more particularly, to such a PCI bus system having latency and shadow timers.
2. Description of the Related Art
It is known in the art to provide a system bus, through which communication can be had between various computer components, including peripheral devices. It is also known that, at any given bus cycle, only one device, termed the master device, can communicate through the system bus. Therefore, in order to control access to the system bus, a device wishing to transmit data must first arbitrate for the bus and receive grant. In conventional systems, the master device will not release the bus until data transmission is completed.
However, the master device may also be forced to release control of the system bus. Such a situation occurs when another device requests bus mastership. If the bus arbiter decides to shift the grant to the requesting device, it may de-assert the grant from the master device and grant mastership to the requesting device. In this situation, the master device has only one cycle left before it must release the bus.
One system which has been developed to enable efficient use of the system bus is the Peripheral Component Interconnect (PCI) architecture. In PCI systems, each device is provided with a latency timer and a predetermined latency value. An exemplary PCI system is shown in FIG. 1. A more detailed explanation of a known PCI system can be found in, for example, PCI Local Bus Specification, Revision 2.0, Copyright 1992, 1993, PCI Special Interest Group, and in PCI to PCI Bridge Architecture Specification, Revision 1.0, 1994 (original issue), PCI Special Interest Group, which are incorporated herein by reference.
With reference to FIG. 1, CPU 10 is connected to cache 20 and host bridge 30. The host bridge 30 is connected to the system memory 40 and the system bus 50. Access to system bus 50 is controlled by bus arbiter 60, which may comprise an integral part of the system bus 50. System bus 50 is used to allow communication between various peripheral devices, and between the peripheral devices and the host bridge. For purpose of illustration, four peripheral devices 100, 200, 300, and 400, are shown in FIG. 1; however, those skilled in the art will understand that the number of devices can vary depending on the particular system arrangement.
Each of the peripheral devices 100, 200, 300, and 400, is connected to the system bus 50 via respective input/output masters 110, 210, 310, and 410, (I/O-DMA master) having respective latency timers 120, 220, 320, and 420, and respective latency values L.sub.1, L.sub.2, L.sub.3, and L.sub.4. Each latency value L.sub.i is generally defined in terms of a certain number of bus cycles. In addition, a pair of REQ# and GRT# lines (not shown) are connected between every respective I/O-DMA master 110, 210, 310, and 410, and the arbiter 60.
For the purpose of illustrating the operation of a PCI system, description will be made of the process wherein peripheral device 100 transfers data to peripheral device 200. A similar process occurs when other peripheral devices attempt to transfer data. In order to transfer data to peripheral device 200, peripheral device 100 must arbitrate for the system bus 50. Therefore, I/O-DMA master 110 sends a request to bus arbiter 60. (The terminology used herein is sometimes generalized. For example, in PCI terminology this step would be the equivalent of device 100 asserting REQ#. Also, in PCI terminology the "#" symbol stands for "asserted low" and it will be used hereinafter to designate the respective PCI signal). If bus arbiter 60 determines that peripheral device 100 may access system bus 50 it sends a grant (GNT# or grant#) to I/O-DMA master 110. At such time, peripheral device 100 may assert frame# by sending the proper command (Read, Write, etc.) and the target's address on the respective bus lines (not shown), and begin data transmission. (Frame# is a PCI command generally indicating that a master device is communicating over the bus). At the same time, latency timer 120 begins to increment.
During the time that peripheral device 100 transmits data, another device, such as, for example, peripheral device 300, may arbitrate for control of system bus 50. Bus arbiter 60 may then decide to de-assert the grant# from the master device 100 and grant mastership to the requesting peripheral device 300. If peripheral device 100 completes the data transmission before latency timer 120 reaches the latency value L.sub.1, then I/O-DMA master 110 will release the system bus 50 and peripheral device 300 will become the master device.
However, if peripheral device 100 did not complete its data transmission, then it may continue transmission until latency timer 120 reaches the latency value L.sub.1. At this point, I/O-DMA master 110 must check whether bus arbiter 60 has de-asserted the grant#. If so, then the master device 100 is allocated one additional cycle to transmit data and, thereafter, I/O-DMA master 110 must release control of system bus 50.
Conversely, if latency timer 120 has reached the latency value L.sub.1, but the arbiter 60 has not de-asserted the grant, the master device 100 may continue data transmission. However, from this cycle forward, the I/O-DMA master 110 must check every cycle whether grant# has been de-asserted, and must release the bus 50 immediately upon determining that the grant# has been de-asserted.
It should be noted that, in the system of FIG. 1, only one of the peripheral devices 100, 200, 300, or 400, can assert frame to act as a master device. That is, at any given time, communication through system bus 50 may be had between only two devices. Therefore, PCI architecture has been implemented in systems having multiple busses, so as to allow several peripheral devices to communicate simultaneously.
An exemplary PCI multiple bridge system is shown in FIG. 2, wherein elements similar to those shown in FIG. 1 have the same reference numerals. For the purpose of this example, only four peripheral devices 100, 200, 300, and 400, and two busses 80, and 90, are shown.
In FIG. 2, host bridge 30 is connected to primary bus 80 and secondary bus 90 through the PCI-PCI bridge 70. For the purpose of this example, peripheral devices 100 and 200 are shown to be connected to primary bus 80 and peripheral devices 300 and 400 are shown to be connected to secondary bus 90. It will be appreciated by those skilled in the art, however, that other arrangements are possible.
Mastership of primary bus 80 and secondary bus 90 is controlled by bus arbiters 82 and 92 respectively. The bus arbiters 82 and 92 are illustrated as two respective parts of PCI-PCI bridge 70; however, they can alternatively be implemented, for example, as a single element, or multiple elements constituting respective integral parts of the primary bus 80 and secondary bus 90, as will be apparent to those skilled in the art.
In the PCI system of FIG. 2, communication between peripheral devices 100 and 200 is performed through the primary bus 80, and communication between the peripheral devices 300 and 400 is performed through secondary bus 90, in a manner similar to that described above with respect to FIG. 1. However, a different procedure is followed when either of peripheral devices 100 and 200, connected to primary bus 80, communicates with either of the peripheral devices 300 or 400, connected to the secondary bus 90. Such a procedure is generally referred to as a two level arbitration. For purpose of demonstration, description will be made with respect to the case where peripheral device 100 wishes to transmit data to peripheral device 300.
In order for peripheral device 100 to transmit data to peripheral device 300, it first must arbitrate for primary bus 80. Accordingly, the I/O-DMA master 110 sends a request (asserts REQ#) to the bus arbiter 82. When the bus arbiter 82 sends the grant#, peripheral device 100 asserts frame# by sending the proper command and the target's address on the respective bus lines (not shown). PCI-PCI bridge 70 recognizes that the target for the address is connected to secondary bus 90 and, accordingly, keeps the master device 100 in a wait state and arbitrates for the secondary bus 90.
Meanwhile, when device 100 receives the grant# from bus 80, latency timer 120 begins to increment. It should be appreciated that, although device 100 has asserted frame#, no data is being transmitted at this time since mastership of secondary bus 90, to which peripheral device 300 is connected, has not been established. However, since latency timer 120 begins to increment from the moment I/O-DMA master 110 asserts frame# of primary bus 80, it is possible that it may reach the latency value L.sub.1 prior to PCI-PCI bus 70 receiving grant# from secondary bus 90.
If the latency value L.sub.1 is reached prior to PCI-PCI bus 70 receiving grant# from secondary bus 90, then the I/O-DMA master 110 would have only one cycle to transfer data before it would be required to release the primary bus 80. As a result, peripheral device 100 would be able to transfer data during only one cycle instead of the number of cycles defined by its latency value L.sub.1. Accordingly, if this situation occurs, only a small part of the data from device 100 would be transferred to the target device 300, i.e. only data corresponding to one cycle. In addition, primary bus 80 and PCI-PCI bridge 70 would be wastefully controlled by peripheral device 100 during the time PCI-PCI bridge 70 arbitrates for secondary bus 90. Since data was transmitted only during one cycle, the wasted period is commensurable with the latency value L.sub.1.
Alternatively, PCI-PCI bridge 70 may receive a grant# from secondary bus 90 before latency timer 120 reaches the latency value L.sub.1 but the remaining time may be insufficient to complete transmission of all the data. Therefore, peripheral devices 100 would transfer data over a period shorter than the number of cycle defined by its latency value L.sub.1. Accordingly, part of the latency value L.sub.1 period would be wastefully allocated to establishing the connection to the target device rather than to data transfer.
Therefore, in order to increase the number of completed transactions, the latency value L.sub.i (i designating any of peripheral devices 100, 200, 300, or 400) may be set at a maximum permissible value. For example, in existing systems it may be set at a maximum of 256 data cycles (the limiting factor being the number of bits in the register). However, should the latency value L.sub.1 be set at such a maximum, it will provide a master device with an unproportionally large share of the total allocable time when the master device is communicating with a device connected to the same bus. As is known to those skilled in the art, certain devices are time sensitive in that they cannot be put in a wait state for too long of a period. Therefore, if a master device asserts frame# during a maximum permissible latency period, such time sensitive devices may not be able to get on the bus and will starve. Such a situation may lead to corruption of data in the starved devices.
Moreover, when a master device that has been allocated the maximum permissible latency is initiating a transaction over the PCI-PCI bridge, part of the latency value is expended on arbitrating for the target's bus. If during the arbitration for the target's bus the latency timer expires, then only one cycle of the maximum permissible latency period would be dedicated to data transmission. Accordingly, in a system where devices are allocated the maximum permissible latency period, each incomplete transaction over the PCI-PCI bridge 70, e.g., when only one data cycle has been used for data transfer, will result in longer wasteful periods.